{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:13:07Z","timestamp":1730272387296,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8351310","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-5","source":"Crossref","is-referenced-by-count":7,"title":["Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm"],"prefix":"10.1109","author":[{"given":"Andrea","family":"Bandiziol","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Werner","family":"Grollitsch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francesco","family":"Brandonisio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matteo","family":"Bassi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roberto","family":"Nonis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pierpaolo","family":"Palestri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942120"},{"key":"ref12","first-page":"410","article-title":"A 16Gb\/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5us","author":"shahramian","year":"2016","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373377"},{"key":"ref14","first-page":"2885","article-title":"A 10-Gb\/s 5-tap DFE\/4-tap FFE transceiver in 90-nm CMOS technology","volume":"12","author":"bulzacchelli","year":"2007","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MIPRO.2016.7522116"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2002.1024421"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417908"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487622"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2740268"},{"article-title":"Wireless Communication In and Around the Car: Status and Outlook - ES3: High-Speed Communications on 4 Wheels: Whats in Your Next Car?","year":"0","author":"endo","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2475996"},{"key":"ref6","first-page":"54","article-title":"Multi-Standard 185fs 0.3-to-28Gb\/s 40dB Backplace Signal Conditioner with Adaptive Pattern-Match 36-Tap DFE and Data- Rate-Adjustment PLL in 28nm CMOS","author":"kawamoto","year":"2015","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2016.7803964"},{"article-title":"Noise considerations for 40\/100GBASE-CR4\/10","year":"0","author":"healey","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2349974"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2477015"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2476016"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417904"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2374176"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2006.382032"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892156"},{"journal-title":"Synopsis Verilog Compiler Simulator 2017 03 Manual","year":"2017","key":"ref23"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351310.pdf?arnumber=8351310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:54:15Z","timestamp":1571691255000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351310\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351310","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}