{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,26]],"date-time":"2025-07-26T09:08:33Z","timestamp":1753520913739,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8351456","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T22:00:05Z","timestamp":1525471205000},"page":"1-5","source":"Crossref","is-referenced-by-count":3,"title":["Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach"],"prefix":"10.1109","author":[{"given":"Davide","family":"Bellizia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe","family":"Scotti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Trifiletti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Security evaluation and optimization of the delay-based dual-rail pre-charge logic in presence of early evaluation of data","author":"bongiovanni","year":"2013","journal-title":"Security and Cryptography (SECRYPT) 2013 International Conference on IEEE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-015-0096-z"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14423-3_11"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards","year":"2007","author":"mangard","key":"ref14"},{"key":"ref15","article-title":"A Power-Balanced Sequential Element for the Delay-based Dual-Rail Precharge Logic Style","volume":"4","author":"bongiovanni","year":"2013","journal-title":"International Journal of Microelectronics and Computer Science"},{"key":"ref16","article-title":"A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards","author":"tiri","year":"0","journal-title":"Proc of ESSCIRC '02"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2016.7529734"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2563322"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85893-5_7"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2286"},{"key":"ref6","article-title":"A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards","author":"tiri","year":"0","journal-title":"Proc of ESSCIRC '02"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2012.6416733"},{"key":"ref7","first-page":"143","author":"tiri","year":"2004","journal-title":"Place and Route for Secure Standard Cell Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-57339-7_5"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2046505"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2017.8093333"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351456.pdf?arnumber=8351456","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:53:12Z","timestamp":1571705592000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351456\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351456","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}