{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T13:35:15Z","timestamp":1725716115031},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,5]]},"DOI":"10.1109\/iscas.2018.8351552","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T22:00:05Z","timestamp":1525471205000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Kernel Aware Warp Scheduler"],"prefix":"10.1109","author":[{"given":"Sen-Chih","family":"Tsai","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Xiang","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Han","family":"Chin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Zhong","family":"Ceng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Ho","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming","author":"park","year":"2016","journal-title":"2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)"},{"key":"ref3","article-title":"Neither more nor less: optimizing thread-level parallelism for GPGPUs","author":"kayiran","year":"2013","journal-title":"Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques"},{"journal-title":"NVIDIA Nvidia's Next Generation CUDA Compute Architecture Fermi","year":"2010","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056031"},{"year":"2011","key":"ref11","article-title":"AMD: Accelerated Parallel Processing TECHNOLOGY, Evergreen Family Instruction Set Architecture, Instruction and Microcode"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750418"},{"journal-title":"CL Offline Compiler and SNACK Web resource","year":"0","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835937"},{"journal-title":"Khronos OpenCL Working Group","article-title":"The OpenCL Specification Version: 2.0","year":"2014","key":"ref7"},{"journal-title":"Understanding Latency Hiding on GPUs","year":"2016","author":"volkov","key":"ref2"},{"journal-title":"The HSA Foundation","article-title":"HSA Programmer's Reference Manual: HSAIL Virtual ISA and Programming Model, Compiler Writer, and Object Format (BRIG) Version 1.0 Final","year":"2015","key":"ref9"},{"journal-title":"GPU performance modeling and optimization Diss","year":"2016","author":"ang","key":"ref1"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351552.pdf?arnumber=8351552","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:51:59Z","timestamp":1571705519000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351552\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351552","relation":{},"subject":[],"published":{"date-parts":[[2018,5]]}}}