{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:14:45Z","timestamp":1730272485181,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,5]]},"DOI":"10.1109\/iscas.2018.8351683","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-5","source":"Crossref","is-referenced-by-count":3,"title":["3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage"],"prefix":"10.1109","author":[{"given":"Chihiro","family":"Matsui","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"Takeuchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2015.7150277"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E100.C.373"},{"journal-title":"Core messaging deck Data access-A new Approach","year":"0","key":"ref12"},{"journal-title":"MSR Cambridge Traces","year":"0","key":"ref13"},{"key":"ref14","first-page":"60","article-title":"Reconfiguarable SCM capacity identification method for SCM\/NAND flash hybrid disaggregated storage","author":"sugiyama","year":"2017","journal-title":"Proc IEEE Int Memory Workshop (IMW)"},{"key":"ref15","first-page":"115","article-title":"ARC: A self-tuning, low overhead replacement cache","author":"megiddo","year":"2013","journal-title":"Proc USENIX Conf File and Storage Technologies (FAST)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838600"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838490"},{"journal-title":"Micron 3D XPoint Technology","year":"0","key":"ref6"},{"key":"ref5","first-page":"46","article-title":"A 20nm 1. 8V 8Gb PRAM with 40MB\/s program bandwidth","author":"choi","year":"2012","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"journal-title":"DRAMeXchange","year":"0","key":"ref8"},{"journal-title":"Storage Class Memory Towards A Disruptively Low-cost Solid-state Non-volatile Memory","year":"0","author":"burr","key":"ref7"},{"journal-title":"Intel Optane Technology","year":"0","key":"ref2"},{"key":"ref1","first-page":"134","article-title":"xl l performacne increase, x6. 9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM\/MLC NAND SSDs by data fragmentation suppression","author":"fujii","year":"0"},{"key":"ref9","first-page":"4ce02-1","article-title":"Optimal memory configuration analysis in tri-hybrid solid-state drives with storae class memory and multi-level cell\/triple-level cell NAND flash memory","volume":"56","author":"matsui","year":"2017","journal-title":"Jpn J Appl Phys (JJAP)"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351683.pdf?arnumber=8351683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:51:03Z","timestamp":1571691063000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351683\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351683","relation":{},"subject":[],"published":{"date-parts":[[2018,5]]}}}