{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:15:19Z","timestamp":1730272519207,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8351801","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T22:00:05Z","timestamp":1525471205000},"page":"1-5","source":"Crossref","is-referenced-by-count":4,"title":["Characterization of an Associative Memory Chip in 28 nm CMOS Technology"],"prefix":"10.1109","author":[{"given":"Alberto","family":"Annovi","sequence":"first","affiliation":[]},{"given":"Giovanni","family":"Calderini","sequence":"additional","affiliation":[]},{"given":"Stefano","family":"Capra","sequence":"additional","affiliation":[]},{"given":"Bruno","family":"Checcucci","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Crescioli","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"De Canio","sequence":"additional","affiliation":[]},{"given":"Giacomo","family":"Fedi","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Frontini","sequence":"additional","affiliation":[]},{"given":"Maroua","family":"Garci","sequence":"additional","affiliation":[]},{"given":"Christos","family":"Gentsos","sequence":"additional","affiliation":[]},{"given":"Takashi","family":"Kubota","sequence":"additional","affiliation":[]},{"given":"Valentino","family":"Liberali","sequence":"additional","affiliation":[]},{"given":"Fabrizio","family":"Palla","sequence":"additional","affiliation":[]},{"given":"Jafar","family":"Shojaii","sequence":"additional","affiliation":[]},{"given":"Calliope-Louisa","family":"Sotiropoulou","sequence":"additional","affiliation":[]},{"given":"Alberto","family":"Stabile","sequence":"additional","affiliation":[]},{"given":"Gianluca","family":"Traversi","sequence":"additional","affiliation":[]},{"given":"Sebastien","family":"Viret","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Tech Rep ATL-COM-DAQ-2017-160","article-title":"Technical Design Report for the Phase-II Up-grade of the ATLAS TDAQ System","year":"2017","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/11\/02\/C02056"},{"article-title":"Memoria CAM","year":"2015","author":"annovi","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/12\/04\/C04013"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463629"},{"key":"ref2","first-page":"s08 003","article-title":"The ATLAS Experiment at the CERN Large Hadron Collider","volume":"3","year":"2008","journal-title":"Journal of Instrumentation"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2011.2179670"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351801.pdf?arnumber=8351801","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:52:14Z","timestamp":1571705534000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351801\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351801","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}