{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,11]],"date-time":"2024-08-11T05:52:37Z","timestamp":1723355557495},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702141","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T21:02:28Z","timestamp":1556744548000},"source":"Crossref","is-referenced-by-count":8,"title":["Exact Synthesis of Boolean Functions in Majority-of-Five Forms"],"prefix":"10.1109","author":[{"given":"Zhufei","family":"Chu","sequence":"first","affiliation":[]},{"given":"Winston","family":"Haaswijk","sequence":"additional","affiliation":[]},{"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[]},{"given":"Yinshui","family":"Xia","sequence":"additional","affiliation":[]},{"given":"Lunyao","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"knuth","year":"2015","journal-title":"The Art of Computer Programming Volume 4 Fascicle 6 Satisfiability"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02777-2_5"},{"key":"ref12","article-title":"Practical SAT-a tutorial on applied satisfiability solving","author":"e\u00e9n","year":"2007","journal-title":"Slides of invited talk at Formal Methods in Computer-Aided Design (FMCAD)"},{"key":"ref13","first-page":"830","article-title":"Busy man’s synthesis: Combinational delay optimization with SAT","author":"soeken","year":"2017","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref14","first-page":"21","article-title":"Exact synthesis for logic synthesis applications with complex constraints","author":"testa","year":"2017","journal-title":"International Workshop on Logic and Synthesis (IWLS)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref16","article-title":"The EPFL logic synthesis libraries","author":"soeken","year":"2018","journal-title":"International Workshop on Logic and Synthesis (IWLS)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref3","article-title":"SAT based exact synthesis using DAG topology families","author":"haaswijk","year":"2018","journal-title":"Desgin Automation Conference (DAC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506566"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref8","first-page":"57","article-title":"The EPFL combinational benchmark suite","author":"amar\u00fa","year":"2015","journal-title":"International Workshop on Logic and Synthesis (IWLS)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1166\/jctn.2010.1517"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664059"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1126\/science.284.5412.289"},{"key":"ref9","first-page":"11","article-title":"Integrating an AIG package, simulator, and SAT solver","author":"mishchenko","year":"2018","journal-title":"International Workshop on Logic and Synthesis (IWLS)"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Sapporo, Japan","start":{"date-parts":[[2019,5,26]]},"end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702141.pdf?arnumber=8702141","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:12:30Z","timestamp":1657854750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702141\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702141","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}