{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:16:27Z","timestamp":1730272587223,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702258","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T21:02:28Z","timestamp":1556744548000},"page":"1-5","source":"Crossref","is-referenced-by-count":11,"title":["High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes"],"prefix":"10.1109","author":[{"given":"Marcel","family":"Correa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bianca","family":"Waskow","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruno","family":"Zatt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Palomino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guilherme","family":"Correa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luciano","family":"Agostini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538911"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1109\/TCSVT.2015.2428571","article-title":"Algorithm and architecture design of the H.265\/HEVC intra encoder","volume":"26","author":"pastuszak","year":"2015","journal-title":"IEEE Trans Circuits Syst Video Technol"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742917"},{"key":"ref13","article-title":"A highly pipelined VLSI architecture for all modes and block size intra prediction in HEVC encoder","author":"liu","year":"2013","journal-title":"IEEE 10th International Conference on ASIC (ASICON)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PCS.2013.6737693"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2012.6466830"},{"key":"ref16","article-title":"A 1062Mpixels\/s 8192x4320p high efficiency video coding (H.265) encoder chip","author":"tsai","year":"2013","journal-title":"Symposium on VLSI Circuits (VLSIC)"},{"year":"0","key":"ref17","article-title":"JCTVC-L1100 Common test conditions and software configurations"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PCS.2018.8456249"},{"year":"2017","key":"ref3","article-title":"Cisco Visual Networking Index: Forecast and Methodology, 2016–2021"},{"key":"ref6","article-title":"A Technical Overview of VP9 - The Latest Open-Source Video Codec","author":"mukherjee","year":"2018","journal-title":"SMPTE Technical Conference and Exhibition"},{"article-title":"AV1 Bitstream & Decoding Process Specification","year":"2018","author":"rivaz","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050702"},{"article-title":"VP9 Bitstream & Decoding Process Specification","year":"2016","author":"grange","key":"ref7"},{"year":"2013","key":"ref2","article-title":"Information technology: High efficiency coding and media delivery in heterogeneous environments – Part 2: High efficiency video coding"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"2702","DOI":"10.1109\/TCSVT.2016.2593618","article-title":"A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC","volume":"27","author":"min","year":"2016","journal-title":"IEEE Trans Circuits Syst Video Technol"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702258.pdf?arnumber=8702258","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:10:13Z","timestamp":1657854613000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702258\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702258","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}