{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:25:46Z","timestamp":1764332746973,"version":"3.44.0"},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702327","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T17:02:28Z","timestamp":1556730148000},"page":"1-5","source":"Crossref","is-referenced-by-count":6,"title":["Bulk Linearization Techniques"],"prefix":"10.1109","author":[{"given":"Alfredo","family":"Arnaud","sequence":"first","affiliation":[{"name":"Electrical Engineering Department, Universidad Católica del Uruguay, Av.8 de Octubre 2738, CP. 11600, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rafael","family":"Puyol","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Universidad Católica del Uruguay, Av.8 de Octubre 2738, CP. 11600, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Denisse","family":"Hardy","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Universidad Católica del Uruguay, Av.8 de Octubre 2738, CP. 11600, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mat\u00edas","family":"Miguez","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Universidad Católica del Uruguay, Av.8 de Octubre 2738, CP. 11600, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joel","family":"Gak","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Universidad Católica del Uruguay, Av.8 de Octubre 2738, CP. 11600, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"MOS capacitor structure and linearization method for reduced variation of the capacitance","author":"haralabidis","year":"2009","journal-title":"U S Patent Application"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880606"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271730"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.2478\/bpasts-2014-0009"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2012.6339423"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.720397"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"762","DOI":"10.1109\/TCSII.2016.2603533","article-title":"A Precision Pseudo Resistor Bias Scheme for the Design of Very Large Time Constant Filters","volume":"64","author":"puddu","year":"2017","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref17","first-page":"270","article-title":"Low-distortion super-GOhm subthreshold-MOS resistors for CMOS neural amplifierss","author":"kassiri","year":"2013","journal-title":"IEEE Biomedical Circuits and Systems Conf Rotterdam the Netherlans"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.906203"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2014.2329233"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4107"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2284002"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SCS.2003.1227121"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el.2018.5482"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008292213687"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.315"},{"key":"ref9","article-title":"Low voltage operational transconductance amplifier circuits","author":"chatterjee","year":"2011","journal-title":"U S Patent"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702327.pdf?arnumber=8702327","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:14:47Z","timestamp":1756754087000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702327\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702327","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}