{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:16:42Z","timestamp":1730272602193,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702333","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T21:02:28Z","timestamp":1556744548000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution"],"prefix":"10.1109","author":[{"given":"Shimpei","family":"Sato","sequence":"first","affiliation":[]},{"given":"Eijiro","family":"Sassa","sequence":"additional","affiliation":[]},{"given":"Yuta","family":"Ukon","sequence":"additional","affiliation":[]},{"given":"Atsushi","family":"Takahashi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1997.600055"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e89-a.4.1005"},{"key":"ref12","first-page":"2383","article-title":"Clock period minimization of semi-synchronous circuits by gate-level delay insertion","volume":"82","author":"yoda","year":"1999","journal-title":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e88-a.4.892"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1994.408825"},{"journal-title":"Computer Architecture Fourth Edition A Quantitative Approach","year":"2006","author":"hennessy","key":"ref15"},{"journal-title":"Stanford integer benchmark suite","year":"1988","author":"hennessy","key":"ref16"},{"key":"ref4","first-page":"549","article-title":"Performance evaluation of various configuration of adder in variable latency circuits with error detection\/correction mechanism","author":"ando","year":"2012","journal-title":"SASIMI 2012 Proceedings"},{"key":"ref3","first-page":"1","article-title":"Performance improvement of general-synchronous circuits by variable latency technique using dynamic timing-error detection","author":"sato","year":"2016","journal-title":"SASIMI 2016 Proceedings"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.23"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.700720"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079410"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375307"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702333.pdf?arnumber=8702333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:16:58Z","timestamp":1657855018000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702333\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702333","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}