{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,25]],"date-time":"2025-08-25T21:10:02Z","timestamp":1756156202002,"version":"3.44.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702456","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T17:02:28Z","timestamp":1556730148000},"page":"1-4","source":"Crossref","is-referenced-by-count":16,"title":["A 20Gb\/s Dual-Mode PAM4\/NRZ Single-Ended Transmitter with RLM Compensation"],"prefix":"10.1109","author":[{"given":"Changho","family":"Hyun","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea"}]},{"given":"Hyeongjun","family":"Ko","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea"}]},{"given":"Joo-Hyung","family":"Chae","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea"}]},{"given":"Hyunkyu","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea"}]},{"given":"Suhwan","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417909"},{"key":"ref3","first-page":"108","article-title":"A fully adaptive 19-to-56Gb\/s PAM-4 wireline transsceiver with a configurable ADC in 16nm FinFET","author":"upadhyaya","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref10","first-page":"60","article-title":"A 16-to-40Gb\/s quarter-rate NRZ\/PAM4 dual-mode transmitter in 14nm CMOS","author":"kim","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref6","first-page":"1","article-title":"A 4-40Gb\/s PAM4 transmitter with output linearity optimization in 65nm CMOS","author":"zheng","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351612"},{"key":"ref5","first-page":"58","article-title":"A 36Gb\/s PAM4 transmitter using an 8b 18GS\/s DAC in 28nm CMOS","author":"nazemi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870425"},{"key":"ref7","article-title":"A 12.8Gb\/s quarter-rate transmitter using a 4:1 overlapped multiplexing driver combined with an adaptive clock phase aligner","author":"chae","year":"0","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref2","first-page":"57","article-title":"High-speed serial link challenges using multi-level signaling","author":"dikahaminjia","year":"2015","journal-title":"Proc 24th IEEE Elect Perform Electron Packag Syst"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2705070"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310258"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702456.pdf?arnumber=8702456","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,25]],"date-time":"2025-08-25T20:29:21Z","timestamp":1756153761000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702456\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702456","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}