{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T04:49:10Z","timestamp":1745988550384,"version":"3.28.0"},"reference-count":42,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702542","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T21:02:28Z","timestamp":1556744548000},"page":"1-5","source":"Crossref","is-referenced-by-count":17,"title":["Memristive Device Based Circuits for Computation-in-Memory Architectures"],"prefix":"10.1109","author":[{"given":"Muath Abu","family":"Lebdeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Uljana","family":"Reinsalud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hoang Anh Du","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephan","family":"Wong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2840446"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2819190"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050962"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538937"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297350"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1209-2"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2014.6880476"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2808468"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.4108\/eai.22-3-2017.152397"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2835572"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.39"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228448"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342278"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173171"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1557\/PROC-803-HH1.1"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180587"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858415"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-017-01481-9"},{"key":"ref27","first-page":"427","article-title":"The programmable logic-in-memory (plim) computer","author":"gaillardon","year":"2016","journal-title":"Proc of the Conference on Design Automation and Test in Europe (DATE)"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1718","DOI":"10.7873\/DATE.2015.1136","article-title":"Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications","author":"said hamdioui","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0092-2"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203479"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"873","DOI":"10.1038\/nature08940","article-title":"memristive switches enable stateful logic operations via material implication","volume":"464","author":"borghetti","year":"2010","journal-title":"Nature"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927083"},{"key":"ref1","article-title":"Future of computer architecture","author":"patterson","year":"2006","journal-title":"Berkeley EECS Annual Research Symposium (BEARS)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2846699"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2016.2547842"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2016.7568411"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3210377.3210657"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2017.8106959"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715020"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2016.2583673"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0092-2"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-017-0006-8"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702542.pdf?arnumber=8702542","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:09:12Z","timestamp":1657854552000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702542\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702542","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}