{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T02:59:35Z","timestamp":1725591575731},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/iscas.2019.8702601","type":"proceedings-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T17:02:28Z","timestamp":1556730148000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits"],"prefix":"10.1109","author":[{"given":"Youngsoo","family":"Song","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinwook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2014.2326622"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1149\/07508.0029ecst"},{"year":"2017","key":"ref10","article-title":"Silvcao Atlas User’s Manual"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.1003757"},{"year":"0","key":"ref11","article-title":"Opencores"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.901273"},{"year":"0","key":"ref12","article-title":"IWLS 2005 Benchmarks"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-TSA.2017.7942493"},{"key":"ref7","first-page":"124","article-title":"Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic","author":"avci","year":"2011","journal-title":"Proc Symp VLSI Tee\/mol"},{"key":"ref2","first-page":"717","article-title":"High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability","author":"suk","year":"2005","journal-title":"Proc Int Electron Devices Meeting"},{"key":"ref9","first-page":"357:1","article-title":"Optimization of standard cell based detailed placement for 16 nm finfet process","author":"du","year":"2014","journal-title":"Proc Des Autom Test Europe Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature10679"}],"event":{"name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2019,5,26]]},"location":"Sapporo, Japan","end":{"date-parts":[[2019,5,29]]}},"container-title":["2019 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682239\/8702066\/08702601.pdf?arnumber=8702601","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,14]],"date-time":"2022-07-14T23:16:58Z","timestamp":1657840618000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8702601\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2019.8702601","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}