{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,26]],"date-time":"2026-06-26T09:39:07Z","timestamp":1782466747726,"version":"3.54.5"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/iscas45731.2020.9180480","type":"proceedings-article","created":{"date-parts":[[2020,9,29]],"date-time":"2020-09-29T13:22:27Z","timestamp":1601385747000},"page":"1-5","source":"Crossref","is-referenced-by-count":5,"title":["Multi-Objective Strategies for Stripped-Functionality Logic Locking"],"prefix":"10.1109","author":[{"given":"Zhaokun","family":"Han","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&#x0026;M University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhammad","family":"Yasin","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&#x0026;M University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeyavijayan J. V.","family":"Rajendran","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&#x0026;M University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1060590.1060669"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176634"},{"key":"ref13","article-title":"Controllability and Observability","author":"kantipudi","year":"2005","journal-title":"ELEC7250-001 VLSI testing"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits","volume":"15","author":"lee","year":"1996","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref4","first-page":"495","article-title":"Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation","author":"imeson","year":"2013","journal-title":"USENIX Security Symposium"},{"key":"ref3","article-title":"Building Block for a Secure CMOS Logic Cell Library","author":"baukus","year":"2012","journal-title":"US Patent"},{"key":"ref6","first-page":"1","article-title":"Removal Attacks on Logic Locking and Camouflaging Techniques","author":"yasin","year":"2018","journal-title":"IEEE Transactions on Emerging Topics in Computing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","article-title":"Differential Power Analysis","author":"kocher","year":"1999","journal-title":"International Cryptology Conference on Advances in Cryptology"},{"key":"ref2","first-page":"291","article-title":"Active Hardware Metering for Intellectual Property Protection and Security","author":"alkabani","year":"2007","journal-title":"USENIX Security Symposium"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"ref1","article-title":"Innovation is at Risk Losses of up to $4 Billion Annually due to IP Infringement","year":"2008"}],"event":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Seville, Spain","start":{"date-parts":[[2020,10,12]]},"end":{"date-parts":[[2020,10,14]]}},"container-title":["2020 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9179985\/9180369\/09180480.pdf?arnumber=9180480","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T21:02:10Z","timestamp":1705352530000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9180480\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas45731.2020.9180480","relation":{},"subject":[],"published":{"date-parts":[[2020,10]]}}}