{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T15:05:38Z","timestamp":1777129538592,"version":"3.51.4"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/iscas45731.2020.9180589","type":"proceedings-article","created":{"date-parts":[[2020,9,29]],"date-time":"2020-09-29T13:22:27Z","timestamp":1601385747000},"page":"1-4","source":"Crossref","is-referenced-by-count":10,"title":["Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors"],"prefix":"10.1109","author":[{"given":"Ckristian","family":"Duran","sequence":"first","affiliation":[{"name":"Integrated Systems Research Group − OnChip, Universidad Industrial de Santander − Colombia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanssel","family":"Morales","sequence":"additional","affiliation":[{"name":"Integrated Systems Research Group − OnChip, Universidad Industrial de Santander − Colombia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Camilo","family":"Rojas","sequence":"additional","affiliation":[{"name":"Integrated Systems Research Group − OnChip, Universidad Industrial de Santander − Colombia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Annachiara","family":"Ruospo","sequence":"additional","affiliation":[{"name":"Politecnico di Torino − Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ernesto","family":"Sanchez","sequence":"additional","affiliation":[{"name":"Politecnico di Torino − Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elkim","family":"Roa","sequence":"additional","affiliation":[{"name":"Integrated Systems Research Group − OnChip, Universidad Industrial de Santander − Colombia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"RISC-V Formal Verification Framework","author":"eda","year":"2019"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2005.856207"},{"key":"ref6","article-title":"Spike RISC-V ISA Simulator","author":"foundation","year":"2019"},{"key":"ref5","first-page":"42","article-title":"End-to-End Verification of Arm Processors with Isa-Formal","volume":"9780","author":"reid","year":"2016","journal-title":"Proceedings of the 2016 International Conference on Computer Aided Verification (CAV’16) ser Lecture Notes in Computer Science"},{"key":"ref8","article-title":"The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 20190608-Priv-MSU-Ratified","author":"waterman","year":"2019","journal-title":"Tech Rep"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-09426-7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714912"},{"key":"ref9","article-title":"Yosys Open SYnthesis Suite","author":"wolf","year":"0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2018.8644818"}],"event":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Seville, Spain","start":{"date-parts":[[2020,10,12]]},"end":{"date-parts":[[2020,10,14]]}},"container-title":["2020 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9179985\/9180369\/09180589.pdf?arnumber=9180589","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T21:03:33Z","timestamp":1705352613000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9180589\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/iscas45731.2020.9180589","relation":{},"subject":[],"published":{"date-parts":[[2020,10]]}}}