{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T07:11:20Z","timestamp":1782544280626,"version":"3.54.5"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/iscas45731.2020.9180771","type":"proceedings-article","created":{"date-parts":[[2020,9,29]],"date-time":"2020-09-29T13:22:27Z","timestamp":1601385747000},"page":"1-5","source":"Crossref","is-referenced-by-count":45,"title":["Customized Posit Adders and Multipliers using the FloPoCo Core Generator"],"prefix":"10.1109","author":[{"given":"Raul","family":"Murillo","sequence":"first","affiliation":[{"name":"Department of Computer Architecture and Automation, Complutense University of Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alberto A.","family":"Del Barrio","sequence":"additional","affiliation":[{"name":"Department of Computer Architecture and Automation, Complutense University of Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guillermo","family":"Botella","sequence":"additional","affiliation":[{"name":"Department of Computer Architecture and Automation, Complutense University of Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866172"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927163"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342187"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351142"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00057"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00029"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2920936"},{"key":"ref18","article-title":"Template-based posit multiplication for training and inferring in neural networks","author":"montero","year":"2019"},{"key":"ref19","article-title":"Posit standard documentation","year":"0"},{"key":"ref4","article-title":"Rethinking floating point for deep learning","author":"johnson","year":"2018"},{"key":"ref3","article-title":"Enabling high performance posit arithmetic applications using hardware acceleration","author":"van dam","year":"2018","journal-title":"Master’s thesis"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2880742"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297391"},{"key":"ref8","article-title":"Posit arithmetic","author":"gustafson","year":"0"},{"key":"ref7","first-page":"203","article-title":"Design of power-efficient FPGA convolutional cores with approximate log multiplier","author":"oliveira","year":"2019","journal-title":"European Symposium on Artificial Neural Networks Computational Intelligence and Machine Learning (ESANN)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3316279.3316285"},{"key":"ref1","article-title":"Beating floating point at its own game: Posit arithmetic","volume":"4","author":"gustafson","year":"2017","journal-title":"Supercomputing Frontiers and Innovations"},{"key":"ref9","article-title":"Survey of floating-point formats","author":"munafo","year":"0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3190339.3190340"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715262"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3316279.3316284"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702349"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3316279.3316282"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00026"}],"event":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Seville, Spain","start":{"date-parts":[[2020,10,12]]},"end":{"date-parts":[[2020,10,14]]}},"container-title":["2020 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9179985\/9180369\/09180771.pdf?arnumber=9180771","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T21:06:32Z","timestamp":1705352792000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9180771\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iscas45731.2020.9180771","relation":{},"subject":[],"published":{"date-parts":[[2020,10]]}}}