{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:51:45Z","timestamp":1775598705861,"version":"3.50.1"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/iscas45731.2020.9181003","type":"proceedings-article","created":{"date-parts":[[2020,9,29]],"date-time":"2020-09-29T13:22:27Z","timestamp":1601385747000},"page":"1-5","source":"Crossref","is-referenced-by-count":16,"title":["A New MRAM-Based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision"],"prefix":"10.1109","author":[{"given":"Hongjie","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, TX, USA"}]},{"given":"Yang","family":"Zhao","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, TX, USA"}]},{"given":"Chaojian","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, TX, USA"}]},{"given":"Yue","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, TX, USA"}]},{"given":"Yingyan","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, TX, USA"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926984"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702206"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2726544"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVDAT.2015.7208057"},{"key":"ref15","first-page":"49","article-title":"Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing","volume":"2","year":"2015","journal-title":"IEEE Transactions on Multi-Scale Computing Systems"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2914009"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2538618"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351561"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref28","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding","author":"han","year":"2015"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2014.81"},{"key":"ref27","article-title":"Critical learning periods in deep neural networks","author":"achille","year":"2017"},{"key":"ref3","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"International Conference on Neural Information Processing Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.eswa.2016.09.040"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3115\/v1\/W15-1515"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/P19-1355"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3225058.3225069"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref9","first-page":"1","article-title":"A multilevel cell STT-MRAM-based computing inmemory accelerator for binary convolutional neural network","volume":"54","author":"pan","year":"2018","journal-title":"IEEE Transactions on Magnetics"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322237"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3225058.3225069"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref26","article-title":"The lottery ticket hypothesis: Finding sparse, trainable neural networks","author":"frankle","year":"2018"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/P19-1355"}],"event":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Seville, Spain","start":{"date-parts":[[2020,10,12]]},"end":{"date-parts":[[2020,10,14]]}},"container-title":["2020 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9179985\/9180369\/09181003.pdf?arnumber=9181003","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T21:04:52Z","timestamp":1705352692000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9181003\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/iscas45731.2020.9181003","relation":{},"subject":[],"published":{"date-parts":[[2020,10]]}}}