{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T09:41:41Z","timestamp":1725702101604},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/iscas45731.2020.9181278","type":"proceedings-article","created":{"date-parts":[[2020,9,29]],"date-time":"2020-09-29T09:22:27Z","timestamp":1601371347000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM"],"prefix":"10.1109","author":[{"given":"Binbin","family":"Liu","sequence":"first","affiliation":[{"name":"State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, U.S.A."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847264"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488748"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240778"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967056"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062232"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744908"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19991511"},{"journal-title":"High-Level Synthesis Blue Book","year":"2010","author":"fingero","key":"ref1"}],"event":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2020,10,12]]},"location":"Seville, Spain","end":{"date-parts":[[2020,10,14]]}},"container-title":["2020 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9179985\/9180369\/09181278.pdf?arnumber=9181278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T16:05:08Z","timestamp":1705334708000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9181278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/iscas45731.2020.9181278","relation":{},"subject":[],"published":{"date-parts":[[2020,10]]}}}