{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T13:50:40Z","timestamp":1774965040717,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,21]],"date-time":"2023-05-21T00:00:00Z","timestamp":1684627200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,21]],"date-time":"2023-05-21T00:00:00Z","timestamp":1684627200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,21]]},"DOI":"10.1109\/iscas46773.2023.10181330","type":"proceedings-article","created":{"date-parts":[[2023,7,21]],"date-time":"2023-07-21T17:19:44Z","timestamp":1689959984000},"page":"1-5","source":"Crossref","is-referenced-by-count":12,"title":["AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration"],"prefix":"10.1109","author":[{"given":"Jonathan","family":"Saussereau","sequence":"first","affiliation":[{"name":"Universite de Bordeaux, Bordeaux INP,Laboratoire IMS,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Camille","family":"Leroux","sequence":"additional","affiliation":[{"name":"Universite de Bordeaux, Bordeaux INP,Laboratoire IMS,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Baptiste","family":"Begueret","sequence":"additional","affiliation":[{"name":"Universite de Bordeaux, Bordeaux INP,Laboratoire IMS,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christophe","family":"Jego","sequence":"additional","affiliation":[{"name":"Universite de Bordeaux, Bordeaux INP,Laboratoire IMS,France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2019.8760205"},{"key":"ref9","author":"waterman","year":"2016","journal-title":"The RISC-V Instruction Set Manual Volume I User-Level ISA Version 2 1"},{"key":"ref4","author":"wolf","year":"0","journal-title":"PicoRV32 - A Size-Optimized RISC-V CPU"},{"key":"ref3","author":"asanovi?","year":"2016","journal-title":"The rocket chip generator"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3457388.3458657"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/358274.358283"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075913"},{"key":"ref10","article-title":"The Case for Open Instruction Set","author":"asanovi?","year":"2014","journal-title":"Microprocessor Peport"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293991"}],"event":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Monterey, CA, USA","start":{"date-parts":[[2023,5,21]]},"end":{"date-parts":[[2023,5,25]]}},"container-title":["2023 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10181241\/10181318\/10181330.pdf?arnumber=10181330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T17:50:37Z","timestamp":1691430637000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10181330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,21]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas46773.2023.10181330","relation":{},"subject":[],"published":{"date-parts":[[2023,5,21]]}}}