{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:12:28Z","timestamp":1725783148141},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,21]],"date-time":"2023-05-21T00:00:00Z","timestamp":1684627200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,21]],"date-time":"2023-05-21T00:00:00Z","timestamp":1684627200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,21]]},"DOI":"10.1109\/iscas46773.2023.10181447","type":"proceedings-article","created":{"date-parts":[[2023,7,21]],"date-time":"2023-07-21T17:19:44Z","timestamp":1689959984000},"page":"1-5","source":"Crossref","is-referenced-by-count":3,"title":["Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect"],"prefix":"10.1109","author":[{"given":"Pratik","family":"Shrestha","sequence":"first","affiliation":[{"name":"Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ioannis","family":"Savidis","sequence":"additional","affiliation":[{"name":"Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","first-page":"1","article-title":"Deep learning using rectified linear units (ReLU)","author":"agarap","year":"2018","journal-title":"ArXiv Preprint"},{"key":"ref12","first-page":"1","article-title":"IEEE standard for integrated circuit (IC) open library architecture (OLA)","year":"2020","journal-title":"IEEE Std 1481&#x2013;2019 (Revision of IEEE Std 1481&#x2013;2009)"},{"key":"ref15","first-page":"1","article-title":"Fast graph representation learning with PyTorch Geometric","author":"fey","year":"2019","journal-title":"ArXiv Preprint"},{"key":"ref14","first-page":"1","article-title":"An overview of gradient descent optimization algorithms","author":"ruder","year":"2016","journal-title":"ArXiv Preprint"},{"key":"ref11","article-title":"IWLS 2005 benchmarks","author":"albrecht","year":"2005","journal-title":"Int Workshop Logic Synthesis"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-63823-8_76"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351885"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aiopen.2021.01.001"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218515"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937457"},{"key":"ref9","first-page":"7","article-title":"From global route to detailed route: ML for fast and accurate wire parasitics and timing prediction","author":"chhabria","year":"2022","journal-title":"Proceedings of the 2022 ACM\/ IEEE Workshop on Machine Learning for CAD (MLCAD)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942063"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03544-w"},{"key":"ref6","first-page":"159","article-title":"Transfer of performance models across analog circuit topologies with graph neural networks","author":"wu","year":"2022","journal-title":"Proceedings of the ACM\/ IEEE Workshop on Machine Learning for CAD (MLCAD)"},{"key":"ref5","first-page":"127","article-title":"Graph representation learning for gate arrival time prediction","author":"shrestha","year":"2022","journal-title":"Proceedings of the ACM\/ IEEE Workshop on Machine Learning for CAD (MLCAD)"}],"event":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2023,5,21]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2023,5,25]]}},"container-title":["2023 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10181241\/10181318\/10181447.pdf?arnumber=10181447","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T17:46:02Z","timestamp":1691430362000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10181447\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,21]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas46773.2023.10181447","relation":{},"subject":[],"published":{"date-parts":[[2023,5,21]]}}}