{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:24:11Z","timestamp":1751091851708},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,28]]},"DOI":"10.1109\/iscas48785.2022.9937513","type":"proceedings-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T20:38:08Z","timestamp":1668199088000},"page":"3279-3283","source":"Crossref","is-referenced-by-count":10,"title":["C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations"],"prefix":"10.1109","author":[{"given":"Yifan","family":"He","sequence":"first","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuxuan","family":"Huang","sequence":"additional","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinshan","family":"Yue","sequence":"additional","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenyu","family":"Sun","sequence":"additional","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[{"name":"Tsinghua University,Dept. of Electronic Engineering,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref11","first-page":"1","article-title":"A 14nm 100kb 2t1r transpose rram with >50&#x00D7; resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme","author":"wang","year":"2021","journal-title":"2021 Symposia on VLSI Technology and Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-00505-5"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063078"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365769"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431412"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131572"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3072200"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075887"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418106"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062953"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474179"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3370748.3406583"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"journal-title":"Neural Network Distiller A Python Package for DNN Compression Research","year":"2019","author":"zmora","key":"ref20"}],"event":{"name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2022,5,27]]},"location":"Austin, TX, USA","end":{"date-parts":[[2022,6,1]]}},"container-title":["2022 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9937201\/9937203\/09937513.pdf?arnumber=9937513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:20:08Z","timestamp":1669666808000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9937513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,28]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iscas48785.2022.9937513","relation":{},"subject":[],"published":{"date-parts":[[2022,5,28]]}}}