{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T08:29:06Z","timestamp":1761294546338,"version":"3.37.3"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,28]]},"DOI":"10.1109\/iscas48785.2022.9937600","type":"proceedings-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T20:38:08Z","timestamp":1668199088000},"page":"2886-2890","source":"Crossref","is-referenced-by-count":2,"title":["A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion"],"prefix":"10.1109","author":[{"given":"Xu","family":"Fu","sequence":"first","affiliation":[{"name":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,201203"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,201203"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhaori","family":"Bi","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,201203"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,201203"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"University of Texas at Dallas,Department of Electrical Engineering,TX,U.S.A"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,201203"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"3873","article-title":"Parallelizing explorationexploitation tradeoffs in gaussian process bandit optimization","volume":"15","author":"desautels","year":"2014","journal-title":"The Journal of Machine Learning Research"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40988-2_15"},{"key":"ref12","first-page":"1","article-title":"An efficient batch constrained Bayesian optimization approach for analog circuit synthesis via multi-objective acquisition ensemble","volume":"pp","author":"zhang","year":"2021","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"article-title":"Computer experiments and global optimization","year":"1997","author":"schonlau","key":"ref13"},{"key":"ref14","article-title":"A Multi-points Criterion for Deterministic Parallel Global Optimization based on Kriging[J]","author":"ginsbourger","year":"2008","journal-title":"Journal of Global Optimization in revision"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/7.4.308"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s10898-011-9678-1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2003.808914"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2012.01.003"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.102664"},{"key":"ref6","article-title":"An artificial neural network assisted optimization system for analog design space exploration","author":"li","year":"2019","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref5","article-title":"Ensemble methods for convex regression with applications to geometric programming based circuit design","author":"hannah","year":"2012","journal-title":"arXiv preprint arXiv 1206 4645"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"148","DOI":"10.1109\/JPROC.2015.2494218","article-title":"Taking the human out of the loop: A review of bayesian optimization","volume":"104","author":"shahriari","year":"2015","journal-title":"Proceedings of the IEEE"},{"article-title":"Using Artificial Neural Networks for Analog Integrated Circuit Design Automation","year":"2019","author":"rosa","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729461"},{"key":"ref9","first-page":"648","article-title":"Batch bayesian optimization via local penalization","author":"gonzalez","year":"2016","journal-title":"Artificial Intelligence and Statistics"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106850"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"169","DOI":"10.1109\/TCAD.2013.2284109","article-title":"GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm","volume":"33","author":"gielen","year":"2014","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems A publication of the IEEE Circuits and Systems Society"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CEC.2014.6900309"}],"event":{"name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2022,5,27]]},"location":"Austin, TX, USA","end":{"date-parts":[[2022,6,1]]}},"container-title":["2022 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9937201\/9937203\/09937600.pdf?arnumber=9937600","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,12]],"date-time":"2022-12-12T19:57:45Z","timestamp":1670875065000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9937600\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,28]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iscas48785.2022.9937600","relation":{},"subject":[],"published":{"date-parts":[[2022,5,28]]}}}