{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:46:14Z","timestamp":1725608774150},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,28]]},"DOI":"10.1109\/iscas48785.2022.9937851","type":"proceedings-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T15:38:08Z","timestamp":1668181088000},"page":"2547-2550","source":"Crossref","is-referenced-by-count":0,"title":["Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology"],"prefix":"10.1109","author":[{"given":"Anil Kumar","family":"Gundu","sequence":"first","affiliation":[{"name":"Hong Kong University of Science and Technology Clear Water Bay,Department of Electronic and Computer Engineering,Kowloon,Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Volkan","family":"Kursun","sequence":"additional","affiliation":[{"name":"Norwegian University of Science and Technology,Department of Electronic Systems,Trondheim,Norway,7034"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2009.5236062"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2193129"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838441"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3143774"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2005","author":"weste","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC52499.2021.9739517"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815583"},{"journal-title":"Victory Process DevEdit ATLAS and Clever User&#x2019;s Manual","year":"0","key":"ref9"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2016","key":"ref1"}],"event":{"name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2022,5,27]]},"location":"Austin, TX, USA","end":{"date-parts":[[2022,6,1]]}},"container-title":["2022 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9937201\/9937203\/09937851.pdf?arnumber=9937851","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T15:21:11Z","timestamp":1669648871000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9937851\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,28]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/iscas48785.2022.9937851","relation":{},"subject":[],"published":{"date-parts":[[2022,5,28]]}}}