{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T02:33:56Z","timestamp":1768012436200,"version":"3.49.0"},"reference-count":35,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002701","name":"Ministry of Education","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002701","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,28]]},"DOI":"10.1109\/iscas48785.2022.9937891","type":"proceedings-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T20:38:08Z","timestamp":1668199088000},"page":"2157-2161","source":"Crossref","is-referenced-by-count":3,"title":["An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning"],"prefix":"10.1109","author":[{"given":"N. Nguyen","family":"Thao N.","sequence":"first","affiliation":[{"name":"National University of Singapore,4 Engineering Drive 3,Department of Electrical and Computer Engineering,Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bharadwaj","family":"Veeravalli","sequence":"additional","affiliation":[{"name":"National University of Singapore,4 Engineering Drive 3,Department of Electrical and Computer Engineering,Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuanyao","family":"Fong","sequence":"additional","affiliation":[{"name":"National University of Singapore,4 Engineering Drive 3,Department of Electrical and Computer Engineering,Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"30","article-title":"Vivado design suite","volume":"5","author":"feist","year":"2012","journal-title":"White Paper"},{"key":"ref32","article-title":"AXI reference guide","author":"xilinx","year":"2011"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2017.12.005"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pcbi.0030031"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2004.383"},{"key":"ref34","year":"2019"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3407197.3407216"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3389\/fninf.2018.00089"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2018.8489326"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7554\/eLife.47314"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/s43588-020-00022-7"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2015.00141"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2834892.2834895"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.81"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3229884.3229894"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2019.2928793"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1152\/jn.00686.2005"},{"key":"ref4","first-page":"82","article-title":"Loihi: A neuromorphic manycore processor with on-chip learning","volume":"38","author":"davies","year":"2018","journal-title":"Micro"},{"key":"ref27","first-page":"1","article-title":"Caspian:A neuromorphic development platform","author":"mitchell","year":"2020","journal-title":"NIC Workshop"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2016.09.071"},{"key":"ref6","first-page":"2651","article-title":"CORDIC-SNN:On-FPGA STDP learning with Izhikevich neurons","volume":"66","author":"heidarpur","year":"2019","journal-title":"IEEE TCAS-I"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1038\/78829"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2018.00665"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2951493"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.26599\/TST.2019.9010019"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294916"},{"key":"ref9","article-title":"Akida brainchip","year":"2019"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474396"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2015.00516"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3296979.3192371"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2017.09.011"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009176"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2017.01.003"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00015"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2017.8123631"}],"event":{"name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Austin, TX, USA","start":{"date-parts":[[2022,5,27]]},"end":{"date-parts":[[2022,6,1]]}},"container-title":["2022 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9937201\/9937203\/09937891.pdf?arnumber=9937891","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:20:22Z","timestamp":1669666822000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9937891\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,28]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/iscas48785.2022.9937891","relation":{},"subject":[],"published":{"date-parts":[[2022,5,28]]}}}