{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,15]],"date-time":"2025-07-15T03:16:22Z","timestamp":1752549382687,"version":"3.37.3"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T00:00:00Z","timestamp":1653696000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006180","name":"Technology Development","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006180","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,28]]},"DOI":"10.1109\/iscas48785.2022.9937947","type":"proceedings-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T20:38:08Z","timestamp":1668199088000},"page":"3289-3293","source":"Crossref","is-referenced-by-count":2,"title":["Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing"],"prefix":"10.1109","author":[{"given":"Naoko","family":"Misawa","sequence":"first","affiliation":[{"name":"The University of Tokyo,Dept. of Electrical Engineering and Information Systems,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenta","family":"Taoka","sequence":"additional","affiliation":[{"name":"The University of Tokyo,Dept. of Electrical Engineering and Information Systems,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chihiro","family":"Matsui","sequence":"additional","affiliation":[{"name":"The University of Tokyo,Dept. of Electrical Engineering and Information Systems,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"Takeuchi","sequence":"additional","affiliation":[{"name":"The University of Tokyo,Dept. of Electrical Engineering and Information Systems,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"119","article-title":"Small Array Area, Memory Error Tolerant ReRAM Computation-in-Memory with Logencoding Simulated Annealing for Combinational Optimization Problems","author":"misawa","year":"2021","journal-title":"Ext Abst of Int Conf Solid State Devices and Mater (SSDM)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492400"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838600"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.3389\/fphy.2014.00005"},{"key":"ref14","first-page":"1","article-title":"Maximum Cut Problem, MAX-CUT","author":"commander","year":"2009","journal-title":"Encyclopedia of Optimization"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401293"},{"journal-title":"Network","year":"0","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2019.8739720"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662517"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IMW48823.2020.9108112"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388847"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242466"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2017.7936321"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IWOFC48002.2019.9078447"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2375200"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062965"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365748"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IMW51353.2021.9439610"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240806"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1063\/1.1699114"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.aba9901"}],"event":{"name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2022,5,27]]},"location":"Austin, TX, USA","end":{"date-parts":[[2022,6,1]]}},"container-title":["2022 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9937201\/9937203\/09937947.pdf?arnumber=9937947","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,12]],"date-time":"2022-12-12T19:57:48Z","timestamp":1670875068000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9937947\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,28]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iscas48785.2022.9937947","relation":{},"subject":[],"published":{"date-parts":[[2022,5,28]]}}}