{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,19]],"date-time":"2024-11-19T18:21:06Z","timestamp":1732040466533,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/iscas51556.2021.9401128","type":"proceedings-article","created":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T21:33:36Z","timestamp":1619559216000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)"],"prefix":"10.1109","author":[{"given":"Kohji","family":"Hosokawa","sequence":"first","affiliation":[]},{"given":"Pritish","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Stefano","family":"Ambrogio","sequence":"additional","affiliation":[]},{"given":"Hsinyu","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Charles","family":"Mackin","sequence":"additional","affiliation":[]},{"given":"Andrea","family":"Fasoli","sequence":"additional","affiliation":[]},{"given":"Alexander","family":"Friz","sequence":"additional","affiliation":[]},{"given":"An","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Luquin","sequence":"additional","affiliation":[]},{"given":"Katherine","family":"Spoon","sequence":"additional","affiliation":[]},{"given":"Geoffrey W.","family":"Burr","sequence":"additional","affiliation":[]},{"given":"Scott C.","family":"Lewis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2017.2716579"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934050"},{"key":"ref12","article-title":"Optimization of Analog Accelerators for Deep Neural Networks Inference (Invited)","author":"fasoli","year":"2020","journal-title":"ISCAS"},{"key":"ref13","first-page":"t8.2","article-title":"Inference of Long-Short Term Memory networks at software-equivalent accuracy using 2.5 M analog Phase Change Memory devices","author":"tsai","year":"2019","journal-title":"VLSI Tech Symp"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993482"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2796379"},{"key":"ref4","first-page":"c3.5","article-title":"A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Training and Inference","author":"fleischer","year":"2018","journal-title":"VLSI Tech Symp"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2871057"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6463\/aac8a5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.5042462"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-018-0180-5"},{"key":"ref2","first-page":"1737","article-title":"Deep learning with limited numerical precision","author":"gupta","year":"2015","journal-title":"ICML"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1038\/nature14539","article-title":"Deep learning","volume":"521","author":"lecun","year":"2015","journal-title":"Nature"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201900026"}],"event":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2021,5,22]]},"location":"Daegu, Korea","end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9401028\/9401051\/09401128.pdf?arnumber=9401128","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:44:02Z","timestamp":1652197442000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9401128\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas51556.2021.9401128","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}