{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:04:15Z","timestamp":1751094255261,"version":"3.37.3"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/iscas51556.2021.9401356","type":"proceedings-article","created":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T21:33:36Z","timestamp":1619559216000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["HSC: A Hybrid Spin\/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy"],"prefix":"10.1109","author":[{"given":"Yan","family":"Huang","sequence":"first","affiliation":[]},{"given":"Erya","family":"Deng","sequence":"additional","affiliation":[]},{"given":"Jinyu","family":"Bai","sequence":"additional","affiliation":[]},{"given":"Qing","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Wang","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Biao","family":"Pan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1039\/C8FD00114F"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180808"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.107"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317872"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS.2019.8771550"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3033023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2375205"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2013.2245911"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.5188\/ijsmer.10.34"},{"key":"ref3","first-page":"525","article-title":"Xnor-net: Imagenet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"European Conference on Computer Vision"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2012.2211892"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2701547"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614639"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2881913"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2976475"},{"article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1","year":"2016","author":"courbariaux","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2439635"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268338"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008536"}],"event":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2021,5,22]]},"location":"Daegu, Korea","end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9401028\/9401051\/09401356.pdf?arnumber=9401356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:44:16Z","timestamp":1652197456000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9401356\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iscas51556.2021.9401356","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}