{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T16:12:07Z","timestamp":1780503127949,"version":"3.54.1"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/iscas51556.2021.9401600","type":"proceedings-article","created":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T17:33:36Z","timestamp":1619544816000},"page":"1-5","source":"Crossref","is-referenced-by-count":14,"title":["A 40nm 1Mb 35.6 TOPS\/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning"],"prefix":"10.1109","author":[{"given":"Yuxin","family":"Zhang","sequence":"first","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sitao","family":"Zeng","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiguo","family":"Zhu","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhaolong","family":"Qin","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chen","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jingjing","family":"Li","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sanfeng","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yajuan","family":"He","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chunmeng","family":"Dou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xin","family":"Si","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qiang","family":"Li","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0288-0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063078"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2017.7993628"},{"key":"ref15","first-page":"171","article-title":"Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence","author":"chang","year":"2018","journal-title":"2018 IEEE Symposium on VLSI Technology"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2424972"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013763"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2924965"},{"key":"ref19","first-page":"1","article-title":"Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks","author":"liu","year":"2018","journal-title":"2018 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC) DAC"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref3","first-page":"1","article-title":"Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks","author":"liu","year":"2018","journal-title":"2018 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC) DAC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062995"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062949"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702542"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056933"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870354"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-00505-5"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2917852"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702401"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2885574"}],"event":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Daegu, Korea","start":{"date-parts":[[2021,5,22]]},"end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9401028\/9401051\/09401600.pdf?arnumber=9401600","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,25]],"date-time":"2025-07-25T17:55:19Z","timestamp":1753466119000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9401600\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iscas51556.2021.9401600","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}