{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T17:50:43Z","timestamp":1772041843272,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/iscas51556.2021.9401608","type":"proceedings-article","created":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T21:33:36Z","timestamp":1619559216000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["SMT-Based Placement for System-on-Chip Design"],"prefix":"10.1109","author":[{"given":"Sebastian","family":"Pointner","sequence":"first","affiliation":[]},{"given":"Sven","family":"Wenzek","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Wille","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817546"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TSMCB.2006.883268"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1109\/VLSI.2008.97","article-title":"An elitist non-dominated sorting based genetic algorithm for simultaneous area and wirelength minimization in vlsi floorplanning","author":"fernando","year":"2008","journal-title":"VLSI Design"},{"key":"ref13","article-title":"Z3: An efficient SMT Solver","author":"de moura","year":"2008","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"ref14","article-title":"Boolector 2.0 system description","author":"niemetz","year":"2014","journal-title":"Journal on Satisfiability Boolean Modeling and Computation"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-89558-1_10"},{"key":"ref16","article-title":"OptiMathSAT: A Tool for Optimization Modulo Theories","author":"sebastiani","year":"2018","journal-title":"Journal of Automated Reasoning"},{"key":"ref17","article-title":"?z - an optimizing smt solver","author":"bj\u00f8rner","year":"2015","journal-title":"In Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-49059-0_14"},{"key":"ref19","first-page":"1","article-title":"SMT-based stimuli generation in the SystemC verification library","author":"wille","year":"2009","journal-title":"Forum on Specification and Design Languages"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203890"},{"key":"ref3","article-title":"Yosys - a free verilog synthesis suite","author":"clifford","year":"2013","journal-title":"2018 Austrochip Workshop on Microelectronics (Austrochip)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2016.7977061"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715126"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382665"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240766"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CCAA.2016.7813739"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270301"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858377"},{"key":"ref20","article-title":"Improved sat-based ATPG: more constraints, better compaction","author":"eggersgl\u00fc\u00df","year":"2013","journal-title":"Int’ l Conf on CAD"},{"key":"ref22","article-title":"LEF\/DEF Language Reference","year":"2009","journal-title":"Tech Rep Version 5 7"},{"key":"ref21","author":"biere","year":"2009","journal-title":"Handbook of Satisfiability"},{"key":"ref24","article-title":"Algorithm as 136: A k-means clustering algorithm","author":"hartigan","year":"1979","journal-title":"Journal of the Royal Statistical Society"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/274535.274546"}],"event":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Daegu, Korea","start":{"date-parts":[[2021,5,22]]},"end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9401028\/9401051\/09401608.pdf?arnumber=9401608","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,25]],"date-time":"2022-12-25T16:16:54Z","timestamp":1671985014000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9401608\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iscas51556.2021.9401608","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}