{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:10:07Z","timestamp":1751094607317,"version":"3.41.0"},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006190","name":"Research and Development","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006190","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100020487","name":"Nature","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100020487","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100020487","name":"Nature","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100020487","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004608","name":"Natural Science Foundation of Jiangsu Province","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004608","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11043458","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["FPGA-Par: An Efficient Algorithm for Elegant Partitioning in Multi-FPGA Systems"],"prefix":"10.1109","author":[{"given":"Hengyue","family":"Gao","sequence":"first","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]},{"given":"Chenyang","family":"Dai","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]},{"given":"Jinlun","family":"Ji","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Electronic Science and Engineering,China"}]},{"given":"Bin","family":"Yan","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Electronic Science and Engineering,China"}]},{"given":"Qiyue","family":"Zhao","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]},{"given":"Jiangtao","family":"Yuan","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]},{"given":"Feng","family":"Li","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]},{"given":"Li","family":"Li","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Electronic Science and Engineering,China"}]},{"given":"Yuxiang","family":"Fu","sequence":"additional","affiliation":[{"name":"Nanjing University,School of Integrated Circuits,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683951"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/800263.809204"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2001576.2001642"},{"article-title":"A Deep Learning Framework for Graph Partitioning","volume-title":"Proc. ICLR","author":"Nazi","key":"ref5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597203"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611974317.5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/11590354_139"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643546"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS202256217.2022.9970882"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISEDA59274.2023.10218647"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643481"},{"article-title":"FPGA-Par: an Adaptive Graph Partitioning Algorithm for Multi-FPGA","year":"2025","author":"Gao","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3120549"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2016.93"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSoC.2013.6675273"},{"article-title":"S2C Benchmark: Circuit Topologies with Multi-dimensional Resources and FPGA Constraints","year":"2025","author":"Gao","key":"ref17"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2025,5,25]]},"location":"London, United Kingdom","end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11043458.pdf?arnumber=11043458","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:37:01Z","timestamp":1751092621000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11043458\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11043458","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}