{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T12:09:52Z","timestamp":1777723792155,"version":"3.51.4"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006410","name":"Analog Devices","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006410","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11043658","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Optimized and Reconfigurable Hardware Design for ASCON AEAD and Hash Standards"],"prefix":"10.1109","author":[{"given":"Islam","family":"Elsadek","sequence":"first","affiliation":[{"name":"The Ohio State University,Electrical and Computer Engineering,Columbus,Ohio,USA"}]},{"given":"Eslam","family":"Tawfik","sequence":"additional","affiliation":[{"name":"The Ohio State University,Electrical and Computer Engineering,Columbus,Ohio,USA"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Lightweight Cryptography: Project Overview"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.6028\/nist.ir.8454"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-021-09398-9"},{"key":"ref4","article-title":"Crypto competitions: CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/iscas48785.2022.9937643"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2024.3434686"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/icecs202256217.2022.9971037"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/jiot.2021.3052184"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/socc56010.2022.9908100"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISDFS60797.2024.10527312"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/PACET60398.2024.10497076"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/iscas48785.2022.9937755"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2024.3522193"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"London, United Kingdom","start":{"date-parts":[[2025,5,25]]},"end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11043658.pdf?arnumber=11043658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:37:33Z","timestamp":1751092653000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11043658\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11043658","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}