{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:30:21Z","timestamp":1781886621178,"version":"3.54.5"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100009950","name":"Ministry of Education","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100009950","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11043670","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Fully-Integrated Differential RRAM Cell Designs with Multi-Level Capability and Enhanced Read Margin"],"prefix":"10.1109","author":[{"given":"Stefan","family":"Pechmann","sequence":"first","affiliation":[{"name":"Technical University of Munich,Chair of Micro-and Nanosystems Technology,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peter","family":"Reichel","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits (IIS),Division Engineering of Adaptive Systems EAS,Dresden,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thorsten","family":"Sp\u00e4tling","sequence":"additional","affiliation":[{"name":"Technical University of Munich,Chair of Micro-and Nanosystems Technology,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amelie","family":"Hagelauer","sequence":"additional","affiliation":[{"name":"Technical University of Munich,Chair of Micro-and Nanosystems Technology,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mtcomm.2023.105356"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2961505"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-020-03299-9"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720557"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IMW56887.2023.10145951"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1063\/1.5082901"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2016.2618425"},{"key":"ref8","article-title":"IHP offers access to memristive technology for edge AI computing or hardware artificial neural networks applications","year":"2021"},{"key":"ref9","article-title":"Memristive Devices","year":"2024"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS58634.2023.10382824"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2019.2931769"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-017-17785-1"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582090"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724674"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DFT56152.2022.9962345"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS45951.2020.9129252"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2016.2646758"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2508034"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1063\/1.5108650"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS60203.2024.10506121"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"London, United Kingdom","start":{"date-parts":[[2025,5,25]]},"end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11043670.pdf?arnumber=11043670","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:45:37Z","timestamp":1751093137000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11043670\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11043670","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}