{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:58:09Z","timestamp":1780444689649,"version":"3.54.1"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11043686","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":3,"title":["A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs"],"prefix":"10.1109","author":[{"given":"Andrea","family":"Galimberti","sequence":"first","affiliation":[{"name":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gabriele","family":"Montanaro","sequence":"additional","affiliation":[{"name":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea","family":"Motta","sequence":"additional","affiliation":[{"name":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Federico","family":"Proverbio","sequence":"additional","affiliation":[{"name":"E4 Computer Engineering,Scandiano,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Davide","family":"Zoni","sequence":"additional","affiliation":[{"name":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3506713"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/access.2023.3288431"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD63220.2024.00108"},{"key":"ref4","first-page":"103257","article-title":"Design-time methodology for optimizing mixed-precision cpu architectures on fpga","volume-title":"Journal of Systems Architecture","volume":"155","author":"Denisov","year":"2024"},{"key":"ref5","first-page":"102476","article-title":"Cost-effective fixed-point hardware support for RISC-V embedded systems","volume-title":"Journal of Systems Architecture","volume":"126","author":"Zoni","year":"2022"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS58634.2023.10382918"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2018.2834439"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3291049"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3593044"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2642708"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/mssc.2016.2546659"},{"key":"ref12","first-page":"991","article-title":"Do OS abstractions make sense on FPGAs?","volume-title":"14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20)","author":"Korolija"},{"key":"ref13","first-page":"967","article-title":"FpgaNIC: An FPGA-based versatile 100gb SmartNIC for GPUs","volume-title":"2022 USENIX Annual Technical Conference (USENIX ATC 22)","author":"Wang"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/fccm48280.2020.00015"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439284"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD63648.2024.00026"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/tc.2021.3075765"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2023.3282172"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/isca.2014.6853210"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2019.2915318"},{"key":"ref21","volume-title":"Memory Systems: Cache, DRAM, Disk","author":"Jacob","year":"2010"},{"key":"ref22","article-title":"AMBA AXI and ACE Protocol Specification Version H.c","author":"Limited","year":"2021"},{"key":"ref23","article-title":"proFPGA quad Motherboard for Multi-FPGA System","year":"2022"},{"key":"ref24","article-title":"proFPGA XCKU115 Kintex UltraScale FPGA Module","year":"2022"},{"key":"ref25","article-title":"proFPGA DDR4 2.5 GB SDRAM Memory Board","year":"2022"},{"key":"ref26","article-title":"UltraScale FPGA Product Tables and Product Selection Guide (XMP102)","year":"2016"},{"key":"ref27","article-title":"EDY4016A - 4Gb: x 16 DDR4 SDRAM","year":"2014"},{"key":"ref28","article-title":"UltraScale Architecture-Based FPGAs Memory IP Product Guide (PG150)","year":"2022"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"London, United Kingdom","start":{"date-parts":[[2025,5,25]]},"end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11043686.pdf?arnumber=11043686","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:00:23Z","timestamp":1751094023000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11043686\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11043686","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}