{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T04:04:25Z","timestamp":1751169865152,"version":"3.41.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11043817","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems"],"prefix":"10.1109","author":[{"given":"Yuyao","family":"Kong","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianwei","family":"Jia","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anni","family":"Lu","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Faaiq","family":"Waqar","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan-Chun","family":"Luo","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hai","family":"Li","sequence":"additional","affiliation":[{"name":"Technology Research, Intel,Exploratory Integrated Circuits,Hillsboro,OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ian","family":"Young","sequence":"additional","affiliation":[{"name":"Technology Research, Intel,Exploratory Integrated Circuits,Hillsboro,OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nphys2900"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/nature10012"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.abh0952"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/s41377-022-01013-1"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365766"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830438"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3319484"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3229437"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3092533"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2498601"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3406325.3451009"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3655673"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218695"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631328"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45625.2022.10019380"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3142896"},{"key":"ref18","first-page":"1","article-title":"Strategy Toward HZO BEOL-FeRAM with Low-Voltage Operation (<1.2 V), Low Process Temperature, and High Endurance by Thickness Scaling","volume-title":"Symposium on VLSI Technology","author":"Tahara"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45741.2023.10413879"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3412631"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454294"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2023.3298739"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3114422"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2025,5,25]]},"location":"London, United Kingdom","end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11043817.pdf?arnumber=11043817","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:54:38Z","timestamp":1751093678000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11043817\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11043817","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}