{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:40:04Z","timestamp":1751096404881,"version":"3.41.0"},"reference-count":2,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11044164","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-1","source":"Crossref","is-referenced-by-count":0,"title":["Live Demonstration: Smart Watchdog Mechanism for Real-time Fault Detection in RISC-V"],"prefix":"10.1109","author":[{"given":"David","family":"Simpson","sequence":"first","affiliation":[{"name":"Ulster University,School of Computing, Engineering and Intelligent Systems,Derry,Northern Ireland, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Harkin","sequence":"additional","affiliation":[{"name":"Ulster University,School of Computing, Engineering and Intelligent Systems,Derry,Northern Ireland, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malachy","family":"McElholm","sequence":"additional","affiliation":[{"name":"Ulster University,School of Computing, Engineering and Intelligent Systems,Derry,Northern Ireland, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liam","family":"McDaid","sequence":"additional","affiliation":[{"name":"Ulster University,School of Computing, Engineering and Intelligent Systems,Derry,Northern Ireland, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"author":"Eshraghian","key":"ref1","article-title":"SNNtorch"},{"author":"Nolting","key":"ref2","article-title":"The NEORV32 RISC-V Processor - Datasheet"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2025,5,25]]},"location":"London, United Kingdom","end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11044164.pdf?arnumber=11044164","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:03:32Z","timestamp":1751094212000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11044164\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":2,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11044164","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}