{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T04:04:18Z","timestamp":1751169858809,"version":"3.41.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,25]],"date-time":"2025-05-25T00:00:00Z","timestamp":1748131200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,25]]},"DOI":"10.1109\/iscas56072.2025.11044281","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T17:42:19Z","timestamp":1751046139000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["A 0.22 pJ\/bit Processing-in-Controller GEMV Macro with Weight Prefetch for Efficient Near-Memory Computing"],"prefix":"10.1109","author":[{"given":"Jie","family":"Yang","sequence":"first","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiapei","family":"Zheng","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siqi","family":"He","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lizhou","family":"Wu","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Mu","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haozhe","family":"Zhu","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liyu","family":"Lin","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qi","family":"Liu","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chixiao","family":"Chen","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731694"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454459"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HCS59251.2023.10254711"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365862"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3200718"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00040"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731711"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00053"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2924240"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2023.3293140"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00029"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00078"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071005"}],"event":{"name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2025,5,25]]},"location":"London, United Kingdom","end":{"date-parts":[[2025,5,28]]}},"container-title":["2025 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11043142\/11042930\/11044281.pdf?arnumber=11044281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:22:58Z","timestamp":1751091778000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11044281\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,25]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas56072.2025.11044281","relation":{},"subject":[],"published":{"date-parts":[[2025,5,25]]}}}