{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:16:58Z","timestamp":1725783418448},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10557909","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["The Design of a Low-latency Tensor Decomposition Algorithm and VLSI Architecture"],"prefix":"10.1109","author":[{"given":"Yu-An","family":"Chen","sequence":"first","affiliation":[{"name":"National Taiwan University of Science and Technology,Electronic and Computer Engineering Dept.,Taipei,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-An","family":"Shen","sequence":"additional","affiliation":[{"name":"National Taiwan University of Science and Technology,Electronic and Computer Engineering Dept.,Taipei,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/GlobalSIP.2018.8646665"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/ELECO47770.2019.8990544"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICICT4SD50815.2021.9396980"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3172895"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCT52962.2021.9657860"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LWC.2021.3123182"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2022.3145341"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISIVC54825.2022.9800729"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/BF02289464"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1137\/S0895479898346995"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937331"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP43922.2022.9746726"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942103"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3032626"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP40776.2020.9054313"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2024,5,19]]},"location":"Singapore, Singapore","end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10557909.pdf?arnumber=10557909","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T06:38:39Z","timestamp":1719988719000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10557909\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10557909","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}