{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,24]],"date-time":"2026-08-24T21:44:33Z","timestamp":1787607873354,"version":"build-2736575974"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558239","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Mismatch calibration strategy for query-driven AER read-out in a memristor-CMOS neuromorphic chip"],"prefix":"10.1109","author":[{"given":"Luis","family":"Camu\u00f1as-Mesa","sequence":"first","affiliation":[{"name":"CSIC and Universidad de Sevilla,Instituto de Microelectrónica de Sevilla (IMSE-CNM),Sevilla,Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Teresa","family":"Serrano-Gotarredona","sequence":"additional","affiliation":[{"name":"CSIC and Universidad de Sevilla,Instituto de Microelectrónica de Sevilla (IMSE-CNM),Sevilla,Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bernab\u00e9","family":"Linares-Barranco","sequence":"additional","affiliation":[{"name":"CSIC and Universidad de Sevilla,Instituto de Microelectrónica de Sevilla (IMSE-CNM),Sevilla,Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/mssc.2019.2922889"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s12200-022-00025-4"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/jproc.2015.2444094"},{"key":"ref7","volume-title":"Analog VLSI and Neural Systems (versi\u00f3n public)","author":"Mead","year":"1989"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1002\/047134608x.w8328"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2011.00073"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2011.00026"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993431"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2083191"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3091437"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2805470"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/jetcas.2022.3207514"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Singapore, Singapore","start":{"date-parts":[[2024,5,19]]},"end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558239.pdf?arnumber=10558239","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T07:54:04Z","timestamp":1719993244000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558239\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558239","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}