{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T18:09:56Z","timestamp":1775066996630,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002367","name":"Chinese Academy of Sciences","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558334","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":4,"title":["High-Utilization GPGPU Design for Accelerating GEMM Workloads: An Incremental Approach"],"prefix":"10.1109","author":[{"given":"Chongxi","family":"Wang","sequence":"first","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Penghao","family":"Song","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haoyu","family":"Zhao","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fuxin","family":"Zhang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jian","family":"Wang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Longbing","family":"Zhang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"key":"ref3","year":"2023","journal-title":"GPT-4 technical report"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541967"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.40"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3058217"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00010"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00071"},{"key":"ref10","volume-title":"Nvidia tesla v100 gpu architecture","year":"2017"},{"key":"ref11","volume-title":"Nvidia turing gpu architecture","year":"2019"},{"key":"ref12","volume-title":"Nvidia a100 tensor core gpu architecture","year":"2020"},{"key":"ref13","article-title":"Dissecting the nvidia volta gpu architecture via microbenchmarking","author":"Jia","year":"2018"},{"key":"ref14","article-title":"Dissecting the nvidia turing t4 gpu via microbenchmarking","author":"Jia","year":"2019"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC55821.2022.9926299"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3217824"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00016"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00071"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2023.3247808"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3136457"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3293883.3295734"},{"key":"ref22","volume-title":"cublas v12.2","year":"2023"},{"key":"ref23","volume-title":"Cutlass v3.2","year":"2023"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835955"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Singapore, Singapore","start":{"date-parts":[[2024,5,19]]},"end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558334.pdf?arnumber=10558334","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T07:57:27Z","timestamp":1719993447000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558334\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558334","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}