{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T16:21:40Z","timestamp":1762273300861,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558457","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["ACNNE: An Adaptive Convolution Engine for CNNs Acceleration Exploiting Partial Reconfiguration on FPGAs"],"prefix":"10.1109","author":[{"given":"Chun-Hsian","family":"Huang","sequence":"first","affiliation":[{"name":"National Taitung University,Dept. of Computer Science and Information Engineering,Taiwan"}]},{"given":"Shao-Wei","family":"Tang","sequence":"additional","affiliation":[{"name":"National Chung Cheng University,Dept. of Computer Science and Information Engineering,Taiwan"}]},{"given":"Pao-Ann","family":"Hsiung","sequence":"additional","affiliation":[{"name":"National Chung Cheng University,Dept. of Computer Science and Information Engineering,Taiwan"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.5555\/2999134.2999257"},{"key":"ref2","article-title":"Faster R-CNN: Towards real-time object detection with region proposal networks","volume":"28","author":"Ren","year":"2015","journal-title":"Advances in Neural Information Processing Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577314"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ipdpsw.2018.00031"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916237"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3033730"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00030"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.91"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080221"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715174"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00043"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ITNEC.2019.8729070"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CEAP.2019.8883473"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00061"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.22"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3242897"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056850"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2017.7966166"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"issue":"11","key":"ref21","first-page":"1","article-title":"Accelerating deep convolutional neural networks using specialized hardware","volume":"2","author":"Ovtcharov","year":"2015","journal-title":"Microsoft Research Whitepaper"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783722"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2017.09.046"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS48704.2020.9184640"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2016.7857144"},{"year":"2022","key":"ref26","article-title":"Vivado design suite user guide - dynamic function exchange UG909(v2020.2)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2962513"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065667"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"article-title":"DNNweaver: From high-level deep network models to FPGA acceleration","volume-title":"Proc. Workshop on Cognitive Architectures","author":"Sharma","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2785257"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2021.104363"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2018.2808319"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2024,5,19]]},"location":"Singapore, Singapore","end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558457.pdf?arnumber=10558457","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T06:36:15Z","timestamp":1719988575000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558457\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558457","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}