{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:04:51Z","timestamp":1751094291185},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000288","name":"Royal Society","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000288","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000781","name":"European Research Council","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010269","name":"Wellcome Trust","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100010269","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558489","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["An FPGA-based, multi-channel, real-time, motion artifact detection technique for fNIRS\/DOT systems"],"prefix":"10.1109","author":[{"given":"Yunjia","family":"Xia","sequence":"first","affiliation":[{"name":"DSIS University College London(UCL),HUB of Intelligent Neuro-Engineering (HUBIN),London,UK"}]},{"given":"Elisabetta Maria","family":"Frijia","sequence":"additional","affiliation":[{"name":"University College London(UCL),DOT-HUB, Department of Medical Physics and Biomedical Engineering,London,UK"}]},{"given":"Rui","family":"Loureiro","sequence":"additional","affiliation":[{"name":"University College London(UCL),Division of Surgery & Interventional Science(DSIS),London,UK"}]},{"given":"Robert J.","family":"Cooper","sequence":"additional","affiliation":[{"name":"University College London(UCL),DOT-HUB, Department of Medical Physics and Biomedical Engineering,London,UK"}]},{"given":"Hubin","family":"Zhao","sequence":"additional","affiliation":[{"name":"DSIS University College London(UCL),HUB of Intelligent Neuro-Engineering (HUBIN),London,UK"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuroimage.2012.03.049"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuroimage.2013.05.004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1117\/1.nph.5.1.011012"},{"volume-title":"LUMO \u2014 Gowerlabs","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/1.nph.8.2.025002"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1117\/1.nph.10.2.023513"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuroimage.2020.117490"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuroimage.2023.120153"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.dcn.2022.101125"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuroimage.2013.04.082"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1117\/1.NPh.3.3.031410"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.3788\/AOS202040.2230002"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1117\/1.NPh.9.4.041406"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1088\/0967-3334\/31\/5\/004"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1117\/1.JBO.20.5.056011"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1080\/00401706.1962.10490022"},{"volume-title":"ALINX AXU3EG or AXU3EGB: Ethernet FPGA development board","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1364\/AO.48.00D280"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2024,5,19]]},"location":"Singapore, Singapore","end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558489.pdf?arnumber=10558489","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T06:41:42Z","timestamp":1719988902000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558489\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558489","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}