{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:16:01Z","timestamp":1730272561333,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558557","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator"],"prefix":"10.1109","author":[{"given":"Josiah","family":"Mendes","sequence":"first","affiliation":[{"name":"National University of Singapore,Department of Electrical and Computer Engineering,Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajesh C.","family":"Panicker","sequence":"additional","affiliation":[{"name":"National University of Singapore,Department of Electrical and Computer Engineering,Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3467967"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/te.2006.879784"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/70593.70602"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/152751.152761"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/142040.142080"},{"issue":"2","key":"ref6","first-page":"238","article-title":"Simr: A simulator for learning computer architecture","volume":"27","author":"Sanchez","year":"2011","journal-title":"International Journal of Engineering Education"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1002\/cae.21699"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CONTROL.2012.6334776"},{"key":"ref9","first-page":"1","article-title":"Does badge-based learning buck the grading curve? an educational experiment in computer architecture","volume-title":"Proceedings of the International Conference on Frontiers in Education: Computer Science and Computer Engineering (FECS)","author":"Jamieson"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TE.2008.930097"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref12","first-page":"3","article-title":"An online tool for teaching design trade-offs in computer architecture","volume-title":"Proc. International Conference on Engineering Education","author":"Beg"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339657"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2001.990670"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1054907.1054909"},{"key":"ref16","article-title":"The RISC-V Instruction Set Manual Volume i: Unprivileged ISA Version 20191213","author":"Waterman","year":"2019","journal-title":"Tech. Rep."},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2019.8760205"},{"article-title":"Western digital rolls-out two new swerv risc-v cores for microcontrollers","year":"2019","author":"Shilov","key":"ref18"},{"volume-title":"E. Systems, Introducing esp32-c3","year":"2020","key":"ref19"},{"volume-title":"Pixel 6: Setting a new standard for mobile security","year":"2021","author":"Kleidermacher","key":"ref20"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/WCAE53984.2021.9707149"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.softx.2022.101105"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3338698.3338891"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2917698"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2024,5,19]]},"location":"Singapore, Singapore","end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558557.pdf?arnumber=10558557","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T06:53:05Z","timestamp":1719989585000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558557\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558557","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}