{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:04:50Z","timestamp":1751094290497},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,19]],"date-time":"2024-05-19T00:00:00Z","timestamp":1716076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,19]]},"DOI":"10.1109\/iscas58744.2024.10558668","type":"proceedings-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T17:22:52Z","timestamp":1719940972000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM"],"prefix":"10.1109","author":[{"given":"Yongliang","family":"Zhou","sequence":"first","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhen","family":"Yang","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiming","family":"Wei","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao","family":"Lin","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saiai","family":"Wu","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenjuan","family":"Lu","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Li","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[{"name":"Anhui University,School of Integrated Circuits,HeFei,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3229828"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3207992"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530881"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CONIT59222.2023.10205733"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICEFEET51821.2022.9848038"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DISCOVER52564.2021.9663628"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IPACT.2017.8244888"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EIECT58010.2022.00058"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362842"},{"key":"ref10","first-page":"1","article-title":"Pentavariate vmin analysis of a subthreshold 10T SRAM bit cell with variation tolerant write and divided bit-line read","author":"Gupta","year":"2018","journal-title":"Circuits and Systems I: Regular Papers, IEEE Transactions on"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2159056"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746310"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586011"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465399"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418031"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2837862"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239320"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3123512"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISICIR.2016.7829751"}],"event":{"name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2024,5,19]]},"location":"Singapore, Singapore","end":{"date-parts":[[2024,5,22]]}},"container-title":["2024 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10557746\/10557828\/10558668.pdf?arnumber=10558668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T07:31:30Z","timestamp":1719991890000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10558668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,19]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/iscas58744.2024.10558668","relation":{},"subject":[],"published":{"date-parts":[[2024,5,19]]}}}