{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:54:32Z","timestamp":1781848472338,"version":"3.54.5"},"reference-count":1,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100018537","name":"National Science and Technology Major Project","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100018537","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,24]]},"DOI":"10.1109\/iscas66217.2026.11562155","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:41Z","timestamp":1781813201000},"page":"1683-1683","source":"Crossref","is-referenced-by-count":0,"title":["Live Demonstration: An Agile FPGA-Overlayed CGRA SoC for High-Efficiency Computing"],"prefix":"10.1109","author":[{"given":"Jiahang","family":"Lou","sequence":"first","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jianrong","family":"Zhang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuan","family":"Dai","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zewei","family":"Zhong","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huan","family":"Lin","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenbo","family":"Yin","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lingli","family":"Wang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132391"}],"event":{"name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Shanghai, China","start":{"date-parts":[[2026,5,24]]},"end":{"date-parts":[[2026,5,28]]}},"container-title":["2026 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11561899\/11561804\/11562155.pdf?arnumber=11562155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:46:08Z","timestamp":1781847968000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11562155\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,24]]},"references-count":1,"URL":"https:\/\/doi.org\/10.1109\/iscas66217.2026.11562155","relation":{},"subject":[],"published":{"date-parts":[[2026,5,24]]}}}