{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:53:01Z","timestamp":1781848381504,"version":"3.54.5"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,24]]},"DOI":"10.1109\/iscas66217.2026.11562201","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:41Z","timestamp":1781813201000},"page":"1167-1171","source":"Crossref","is-referenced-by-count":0,"title":["An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM"],"prefix":"10.1109","author":[{"given":"Deyang","family":"Yu","sequence":"first","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chenchen","family":"Liu","sequence":"additional","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chuanjie","family":"Zhang","sequence":"additional","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiao","family":"Fang","sequence":"additional","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2019.8697354"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2019.2897076"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3203583"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3001526"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3092533"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC57769.2023.10321880"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401723"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366045"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2819190"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268808"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3695053.3731089"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCASAI.2024.3452649"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC53450.2021.9567807"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218578"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-04196-6"},{"key":"ref16","first-page":"1","article-title":"Series-parallel hybrid SOT-MRAM computing-in-memory macro with multi-method modulation for high area and energy efficiency","volume-title":"Proc. 61st ACM\/IEEE Design Automation Conf. (DAC)","author":"Huang"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2987439"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776485"},{"key":"ref19","first-page":"1099","article-title":"ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses","volume-title":"Proceedings of the 59th ACM\/IEEE Design Automation Conference","author":"Li"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC54400.2022.9939654"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2015.00376"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2023.3321107"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3352729"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3194918"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT62049.2024.10831416"}],"event":{"name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Shanghai, China","start":{"date-parts":[[2026,5,24]]},"end":{"date-parts":[[2026,5,28]]}},"container-title":["2026 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11561899\/11561804\/11562201.pdf?arnumber=11562201","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:30:34Z","timestamp":1781847034000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11562201\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,24]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iscas66217.2026.11562201","relation":{},"subject":[],"published":{"date-parts":[[2026,5,24]]}}}