{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T06:50:34Z","timestamp":1781851834811,"version":"3.54.5"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,24]]},"DOI":"10.1109\/iscas66217.2026.11562639","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:41Z","timestamp":1781813201000},"page":"4749-4753","source":"Crossref","is-referenced-by-count":0,"title":["A FeFET-based Approximate DCIM Integrating Multiplication and OR Addition In-Bitcell"],"prefix":"10.1109","author":[{"given":"Jangseok","family":"Yu","sequence":"first","affiliation":[{"name":"Korea University,School of Electrical Engineering,Seoul,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Taehwan","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea University,School of Electrical Engineering,Seoul,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seunghwa","family":"Hyun","sequence":"additional","affiliation":[{"name":"Korea University,School of Electrical Engineering,Seoul,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jongsun","family":"Park","sequence":"additional","affiliation":[{"name":"Korea University,School of Electrical Engineering,Seoul,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365766"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/tcsii.2023.3241446"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3209872"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2923745"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2025.3612452"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265014"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2025.3530637"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS59952.2024.10595967"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731659"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3304752"}],"event":{"name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Shanghai, China","start":{"date-parts":[[2026,5,24]]},"end":{"date-parts":[[2026,5,28]]}},"container-title":["2026 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11561899\/11561804\/11562639.pdf?arnumber=11562639","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:50:56Z","timestamp":1781848256000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11562639\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,24]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas66217.2026.11562639","relation":{},"subject":[],"published":{"date-parts":[[2026,5,24]]}}}