{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:52:56Z","timestamp":1781848376503,"version":"3.54.5"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003399","name":"Science and Technology Commission of Shanghai Municipality","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003399","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100008838","name":"Shanghai Municipal Commission of Economy and Informatization","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100008838","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,24]]},"DOI":"10.1109\/iscas66217.2026.11562658","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:41Z","timestamp":1781813201000},"page":"1457-1461","source":"Crossref","is-referenced-by-count":0,"title":["Layout-Aware Standard Cell Synthesis via Reparameterization Multi-Task Bayesian Optimization"],"prefix":"10.1109","author":[{"given":"Zhouyang","family":"Wu","sequence":"first","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ruiyu","family":"Lyu","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Keren","family":"Zhu","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiang","family":"Wang","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhaori","family":"Bi","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Fudan University,College of Integrated Circuits &#x0026; Micro-Nano Electronics"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2565871"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114822"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/3477.678649"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.55180"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896468"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2001.938512"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.918210"},{"key":"ref8","first-page":"89","article-title":"DTCO exploration for efficient standard cell power rails","volume-title":"Design-Process-Technology Co-optimization for Manufacturability XII","volume":"10588","author":"Chava","year":"2018"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720656"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3632409.3640475"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137264"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3698364.3709126"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2448675"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114880"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.365122"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203890"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3037885"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586188"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3390\/electronics14030529"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.52202\/068431-0927"}],"event":{"name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Shanghai, China","start":{"date-parts":[[2026,5,24]]},"end":{"date-parts":[[2026,5,28]]}},"container-title":["2026 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11561899\/11561804\/11562658.pdf?arnumber=11562658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:28:18Z","timestamp":1781846898000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11562658\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,24]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iscas66217.2026.11562658","relation":{},"subject":[],"published":{"date-parts":[[2026,5,24]]}}}