{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T06:51:16Z","timestamp":1781851876034,"version":"3.54.5"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,24]],"date-time":"2026-05-24T00:00:00Z","timestamp":1779580800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003009","name":"Science and Technology Development Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003009","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,24]]},"DOI":"10.1109\/iscas66217.2026.11562749","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:41Z","timestamp":1781813201000},"page":"4598-4602","source":"Crossref","is-referenced-by-count":0,"title":["Performance-Aware Design Space Exploration for Chiplet-Based Cortical Simulation Processors Considering Area Constraint"],"prefix":"10.1109","author":[{"given":"Fanxi","family":"Yang","sequence":"first","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi","family":"Zheng","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lufei","family":"Fan","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qi","family":"Jiang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tianhao","family":"Li","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xun","family":"He","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Li-Rong","family":"Zheng","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhuo","family":"Zou","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Future Information Technology,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1093\/cercor\/bhs358"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1093\/cercor\/bhad512"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.neures.2024.11.005"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/s43588-021-00184-y"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.7554\/eLife.97602.3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2020.11.013"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-024-01126-y"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-023-3926-8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3695053.3731101"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10827-007-0038-6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247947"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3695053.3731045"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2885536"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3665314.3680473"}],"event":{"name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Shanghai, China","start":{"date-parts":[[2026,5,24]]},"end":{"date-parts":[[2026,5,28]]}},"container-title":["2026 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11561899\/11561804\/11562749.pdf?arnumber=11562749","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:57:15Z","timestamp":1781848635000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11562749\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,24]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas66217.2026.11562749","relation":{},"subject":[],"published":{"date-parts":[[2026,5,24]]}}}