{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T16:40:45Z","timestamp":1755794445882,"version":"3.44.0"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/iscc.2015.7405586","type":"proceedings-article","created":{"date-parts":[[2016,2,15]],"date-time":"2016-02-15T19:54:13Z","timestamp":1455566053000},"page":"637-642","source":"Crossref","is-referenced-by-count":0,"title":["Digital reconstruction stage of parallel FBD sigma delta ADC implementation based on programmable digital oscillator in SDR receiver"],"prefix":"10.1109","author":[{"given":"Rihab","family":"Lahouli","sequence":"first","affiliation":[{"name":"GRESCOM Research Lab., SUP'COM, University of Carthage, Tunisia Cit\u00e9 Technologique des Communications, 2083 El Ghazala, Ariana"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manel","family":"Ben-Romdhane","sequence":"additional","affiliation":[{"name":"GRESCOM Research Lab., SUP'COM, University of Carthage, Tunisia Cit\u00e9 Technologique des Communications, 2083 El Ghazala, Ariana"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chiheb","family":"Rebai","sequence":"additional","affiliation":[{"name":"GRESCOM Research Lab., SUP'COM, University of Carthage, Tunisia Cit\u00e9 Technologique des Communications, 2083 El Ghazala, Ariana"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominique","family":"Dallet","sequence":"additional","affiliation":[{"name":"IMS Research Lab., University of Bordeaux, Bordeaux INP ENSEIRB-MATMECA, France, 351 Cours de la Lib\u00e9ration, B\u00e2timent A31, 33405 Talence Cedex"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/I2MTC.2014.6860901"},{"key":"ref11","article-title":"Digital reconstruction stage of the FBD $\\Sigma\\Delta$-based ADC architecture for multistandard receiver","author":"lahouli","year":"2014","journal-title":"20th IMEKO TC4 Int Workshop on ADC Modelling and Testing Research on Electric and Electronic Meas for the Economic Upturn"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2172527"},{"journal-title":"UMTS UE Radio Transmission and Reception (FDD) 3GPP TS 25 101 Version 5 2 0 Release 5 ETSI","year":"2002","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20040198"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"118","DOI":"10.1109\/TCSII.2003.810488","article-title":"A time-interleaved parallel $\\Delta\\Sigma$ A\/D converter","volume":"50","author":"eshraghi","year":"2003","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Proc"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.823663"},{"key":"ref6","article-title":"Bandpass\/wideband ADC architecture using parallel delta sigma modulators","author":"beydoun","year":"2006","journal-title":"Proceedings of the 14th European Signal Processing Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/82.476175"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-008-9274-6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2009.5290513"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571974"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/62.210638"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342483"}],"event":{"name":"2015 IEEE Symposium on Computers and Communication (ISCC)","start":{"date-parts":[[2015,7,6]]},"location":"Larnaca, Cyprus","end":{"date-parts":[[2015,7,9]]}},"container-title":["2015 IEEE Symposium on Computers and Communication (ISCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7397314\/7405441\/07405586.pdf?arnumber=7405586","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T18:17:30Z","timestamp":1755281850000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7405586\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscc.2015.7405586","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}