{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:21:54Z","timestamp":1730272914219,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/iscc.2018.8538753","type":"proceedings-article","created":{"date-parts":[[2018,11,20]],"date-time":"2018-11-20T01:49:31Z","timestamp":1542678571000},"page":"00940-00945","source":"Crossref","is-referenced-by-count":0,"title":["Performance-Aware Energy-Efficient Processes Grouping for Embedded Platforms"],"prefix":"10.1109","author":[{"given":"Paulo Silas Severo","family":"de Souza","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wagner dos Santos","family":"Marques","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcelo da Silva","family":"Conterato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tiago Coelho","family":"Ferreto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabio Diniz","family":"Rossi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522302"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MESA.2006.297010"},{"key":"ref13","first-page":"97","author":"jahnich","year":"2007","journal-title":"Towards dynamic load balancing for distributed embedded automotive systems"},{"key":"ref14","first-page":"25","article-title":"Load-balancing for improving user responsiveness on multicore embedded systems","author":"lim","year":"2012","journal-title":"Proceedings of the Linux Symposium"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2012.6322885"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1155\/2014\/101529"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050515"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169024"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"278","DOI":"10.1145\/173682.165163","article-title":"Limitations of cache prefetching on a bus-based multiprocessor","volume":"21","author":"tullsen","year":"1993","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/71.954620"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.181"},{"key":"ref7","volume":"28","author":"zilles","year":"2000","journal-title":"Understanding the backward slices of performance degrading instructions"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763052"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iThings\/CPSCom.2011.11"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/76.856455"}],"event":{"name":"2018 IEEE Symposium on Computers and Communications (ISCC)","start":{"date-parts":[[2018,6,25]]},"location":"Natal","end":{"date-parts":[[2018,6,28]]}},"container-title":["2018 IEEE Symposium on Computers and Communications (ISCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8510755\/8538441\/08538753.pdf?arnumber=8538753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T19:11:53Z","timestamp":1643224313000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8538753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscc.2018.8538753","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}