{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,24]],"date-time":"2025-09-24T09:04:20Z","timestamp":1758704660224,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,7,9]]},"DOI":"10.1109\/iscc58397.2023.10217831","type":"proceedings-article","created":{"date-parts":[[2023,8,28]],"date-time":"2023-08-28T17:46:48Z","timestamp":1693244808000},"page":"1287-1292","source":"Crossref","is-referenced-by-count":3,"title":["A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design"],"prefix":"10.1109","author":[{"given":"Parisa","family":"Rahimi","sequence":"first","affiliation":[{"name":"School of Physics, Engineering, and Computer Science. University of Hertfordshire ALI0 9AB Hatfield,Networks, Security and Systems Research Group,Hertfordshire,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Myasar","family":"Tabany","sequence":"additional","affiliation":[{"name":"School of Physics, Engineering, and Computer Science. University of Hertfordshire ALI0 9AB Hatfield,Networks, Security and Systems Research Group,Hertfordshire,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seyedali","family":"Pourmoafi","sequence":"additional","affiliation":[{"name":"School of Physics, Engineering, and Computer Science. University of Hertfordshire ALI0 9AB Hatfield,Networks, Security and Systems Research Group,Hertfordshire,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","first-page":"304","article-title":"High speed NP-CMOS and multi-output dynamic full adder cells","author":"mirzaee","year":"2010","journal-title":"International Journal of Electrical and Electronics Engineering 4 4"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.06.005"},{"key":"ref15","first-page":"194","article-title":"Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI","author":"pashaki","year":"2016","journal-title":"INTEGRATION the VLSIjournal"},{"key":"ref14","first-page":"74","article-title":"A New Technique for Enhancing Performance in Full Adder Circuit","volume":"6","author":"uma","year":"0","journal-title":"second International Conference on Communication Computing & Security [ICCCS-2012 Procedia Technology"},{"key":"ref20","first-page":"133","article-title":"A New Low Power Dynamic Full Adder Cell Based on Majority Function","volume":"4","author":"foroutan","year":"2008","journal-title":"World Applied Sciences Journal"},{"key":"ref11","first-page":"808","article-title":"A new full swing full adder based on a new logic approach","volume":"11","author":"ghadiry","year":"2010","journal-title":"World Applied Sciences Journal"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.21272\/jnep.8(4(2)).04061"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.06.004"},{"key":"ref1","article-title":"A 4-bit CMOS Full Adder of I-bit Hybrid 13T Adder with A New SUM Circuit","author":"shing jie","year":"0","journal-title":"IEEE Student Conference on Research and Development (SCOReD)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.01.003"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1016\/j.mejo.2008.08.020","article-title":"Two new low-power Full Adders based on majority-not gates","volume":"40","author":"keivan","year":"2009","journal-title":"Microelectronics Journal"},{"key":"ref19","first-page":"255","article-title":"Design of 64-bit Full Adder by using Dynamic Feedthrough Logic","volume":"2","author":"vishwakarma","year":"2012","journal-title":"International Journal of Emerging Technology and Advanced Engineering"},{"key":"ref18","first-page":"3198","article-title":"Low Power Dynamic CMOS Full-Adder Cell","volume":"6","author":"foroutan","year":"2015","journal-title":"International Journal of Computer Science and Information Technologies"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1515\/eletel-2016-0045"},{"key":"ref7","first-page":"87","article-title":"A Power-Efficient Method for Digital Circuits","volume":"1","author":"kunal","year":"2012","journal-title":"International Journal of Advanced Electrical and Electronics Engineering (IJAEEE)"},{"key":"ref9","first-page":"153","article-title":"Design of New Low-Power High-Performance Full Adder with New XOR-XNOR Circuit","author":"jalalian","year":"2015","journal-title":"International Congress on Technology Communication and Knowledge (ICTCK)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.jestch.2015.09.006"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICTCK.2015.7582650"},{"key":"ref6","first-page":"285","article-title":"Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications","volume":"37","author":"jalalian","year":"2015","journal-title":"Ciencia & Natura"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.jestch.2015.10.001"}],"event":{"name":"2023 IEEE Symposium on Computers and Communications (ISCC)","start":{"date-parts":[[2023,7,9]]},"location":"Gammarth, Tunisia","end":{"date-parts":[[2023,7,12]]}},"container-title":["2023 IEEE Symposium on Computers and Communications (ISCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10217219\/10217829\/10217831.pdf?arnumber=10217831","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T17:50:22Z","timestamp":1695664222000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10217831\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,9]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iscc58397.2023.10217831","relation":{},"subject":[],"published":{"date-parts":[[2023,7,9]]}}}